The invention lies in the semiconductor technology field. More specifically, the invention pertains to a method for fabricating a patterned metal-containing layer on a semiconductor wafer.
Various methods for patterning metal-containing layers, such as for example a platinum layer, are known. For the purpose, a platinum layer that is provided on a semiconductor component is patterned by way of a mask which contains silicon oxide. A selectivity between platinum and silicon oxide of more than 0.6:1 is typically achieved. The etching of the platinum layer by means of the etching mask which contains silicon oxide may be carried out, for example, at temperatures of around approximately 300xc2x0 C. However, the prior art does not disclose any suitable method which could allow the silicon oxide mask used for patterning the platinum layer to be removed from the patterned platinum layer. This is particularly difficult because there is a silicon oxide layer arranged underneath and laterally adjoining the patterned platinum electrode.
Consequently, removal of the silicon-oxide-containing etching mask would lead to undesirable removal of material from the silicon oxide layer arranged beneath and laterally next to the platinum layer, which could, for example, result in undercut etching of the platinum electrode.
By way of example, the silicon oxide layer could be removed selectively with respect to the platinum electrode with a dry or a wet etching step. A further possibility consists in using a doped silicate glass, such as for example PSG (phospho-silicate glass) or BSG (borosilicate glass). The doped silicate glasses can be etched selectively with respect to a silicon oxide layer arranged beneath the platinum layer, for example with hydrofluoric acid. However, the use of a doped silicate glass brings with it the drawback that this glass has a lower etching selectivity during the patterning of the platinum layer. Furthermore, a semiconductor fabrication installation for depositing a doped silicate glass is relatively expensive.
It has furthermore become known that a silicon nitride mask can be used instead of an etching mask which contains silicon oxide in order to pattern the platinum layer. However, the silicon nitride mask has the serious drawback of having very low etching selectivity during patterning of the platinum layer using standard chlorine-containing gases.
It is also known that organic films that are applied by means of spin-on methods can be used as an etching mask for the patterning of a platinum layer. That process is described, for example, in the commonly assigned, copending application Ser. No. 09/128,389, and published German patent application DE 197 33 391 A1. It is a drawback of that solution that the etching methods using organic etching masks to pattern the platinum layer are relatively expensive.
It is accordingly an object of the invention to provide a method of fabricating a structured metal-containing layer on a semiconductor wafer, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an improved method for patterning a metal-containing layer which is particularly suitable for protecting a ferroelectric, applied in a subsequent process step, from hydrogen diffusion.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a patterned metal-containing layer on a semiconductor wafer, which comprises the following steps:
providing a substrate;
forming a metal-containing layer on the substrate;
forming a mask layer on the metal-containing layer;
patterning the mask layer with a lithographically fabricated mask to form a patterned mask layer;
patterning the metal-containing layer, which contains platinum, with the patterned mask layer to form an electrode;
depositing a protective layer, containing silicon nitride, on the patterned mask layer and on the substrate; and
chemically-mechanically polishing the protective layer and the patterned mask layer, to thereby remove the protective layer and the patterned mask layer from the metal-containing layer and thereby uncovering the metal-containing layer, or the electrode.
The method according to the invention for the patterning of a metal-containing layer has the advantage over the prior art that the mask layer used to pattern the metal-containing layer is removed by means of chemical mechanical polishing (CMP). The electrode is advantageously uncovered by the CMP step, so that a layer which is subsequently applied can be applied directly to the electrode. By way of example, the protective layer which is deposited prior to the CMP step is arranged on the electrode and laterally adjoining the electrode. After the CMP step, the protective layer remains laterally next to the electrode, where it can fulfill further functions: for example, the protective layer is suitable for acting as a diffusion barrier to oxygen. Furthermore, the protective layer can reduce the diffusion of hydrogen.
In accordance with an added mode of the inventive method, a barrier layer is applied to the substrate prior to the application of the electrode. The barrier layer advantageously serves as a diffusion barrier for oxygen or metals which could diffuse from the electrode into the contact.
In accordance with an additional mode of the novel method, the following steps are defined:
the barrier layer is patterned by means of an etching mask;
the protective layer is deposited on the etching mask, the barrier layer and the substrate;
the protective layer and the etching mask are removed from the barrier layer by means of chemical mechanical polishing and the barrier layer is uncovered, so that the barrier is laterally encapsulated by the protective layer; and
the electrode is then deposited on the barrier layer and the protective layer.
In this way, the barrier layer of the electrode and the laterally arranged protective layer is protected from the etchant used in isotropic etching.
In accordance with another feature of the invention, a planarization layer is deposited on the protective layer prior to the chemical mechanical polishing. The planarization layer is advantageously suitable for filling up the depressions and ditches in the protective layer and mechanically stabilizing the protective layer, so that mechanical defects are avoided during the subsequent CMP step.
In accordance with a further feature of the method according to the invention a contact, on which the electrode is formed, is arranged in the substrate. By way of example, the contact is suitable for making electrical contact with the electrode formed from the metal-containing layer.
Furthermore, according to the invention, there is provision for the barrier layer to contain titanium or titanium nitride or tantalum or tantalum nitride or tantalum silicon nitride or iridium or iridium oxide. Said materials are advantageously suitable for use as a barrier layer.
A further configuration of the method according to the invention provides for an insulation layer to be formed on the electrode, the insulation layer comprising a ferroelectric material. A ferroelectric material advantageously allows a ferroelectric memory cell to be formed.
A further method step provides for the substrate to contain silicon oxide or for the contact to contain polycrystalline silicon or for the mask layer to contain silicon oxide or for the planarization layer to contain silicon oxide. Said materials are advantageously suitable for forming the corresponding layers.
In accordance with a concomitant feature of the invention, the mask layer has a surface which is remote from the substrate and a side wall which is arranged perpendicular to the surface of the substrate, the protective layer is applied by way of targeted deposition, so that the protective layer is preferentially deposited on the surface of the substrate and on the surface of the mask layer and is deposited in a reduced thickness on the side wall of the mask layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a patterned metal-containing layer on a semiconductor wafer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.